Dielectric layers and metal electrodes are important for the performance and functionality of microelectronic devices such as transistors and memory capacitors. For example, the gate dielectric layer and gate electrode are vital components that are necessary for the operation of a metal-oxide-semiconductor field-effect transistor (MOSFET). Likewise, a dielectric layer and an inner electrode are needed in a dynamic random-access memory (DRAM) trench capacitor, where they are used for storage of charge and access to the charge stored within the capacitor. The selection of materials and deposition processes for these and other dielectric layers and metal electrodes gains importance as microelectronic design rules shrink in an effort to increase device density and functionality.
MOSFETs have traditionally incorporated silicon dioxide (SiO2) or silicon oxynitride (SiON) materials as gate dielectrics, and heavily doped polysilicon as gate electrodes. However, device scaling is quickly reaching the point where these materials will be inadequate to serve their intended purposes. In an effort to increase gate capacitance (and therefore device speed and performance), the SiO2 or SiON gate dielectric layers have been scaled down to thicknesses of 1-1.5 nm. At these physical thicknesses, carrier tunneling through the gate dielectric can lead to an elevated gate leakage current in the device and high power dissipation in the circuit. Thus, gate dielectric layers with higher capacitance are needed, without a reduction in physical thickness. This requirement necessitates the use of dielectric materials with higher dielectric constants (i.e., permittivities) than that of SiO2 (k=3.9). These high-k materials have dielectric constants higher than 3.9, preferably greater than or equal to 9, and in some instances greater than or equal to 25.
Another motivation for the use of alternative gate dielectric materials is the increasing level of interest in non-traditional (i.e., non-silicon) MOSFET channel materials. Such alternative channel materials may have higher intrinsic carrier mobilities and therefore improve device speed. While SiO2 and SiON form high quality interfaces with silicon (Si), however, this is frequently not the case with alternative channel materials such as germanium (Ge), III-V materials such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium antimonide (GaSb), gallium nitride (GaN), and indium antimonide (InSb), or II-VI materials such as zinc selenide (ZnSe) or zinc oxide (ZnO). Thus, high-k gate dielectrics are needed not only to decrease gate leakage and increase gate capacitance, but also to form high-quality interfaces with Si or non-silicon channel materials.
Scaling of DRAM trench capacitors also necessitates the use of high-k dielectrics. To store more charge in a particular physical chip area, capacitor surface area (i.e., the trench depth and aspect ratio of depth to width) should be increased, as should the dielectric constant of the capacitor dielectric layer. Thus, a move from SiO2 or SiON to high-k dielectrics is desirable. For this application, these high-k materials have dielectric constants higher than 3.9, preferably greater than or equal to 9, and in some instances greater than or equal to 25.
The replacement of heavily doped polysilicon as an electrode material is also important for future improvements in device performance. As device geometries scale, issues of gate resistance and polysilicon depletion limit the effectiveness of polysilicon as an electrode material. Additionally, many emerging device geometries and concepts (e.g., ultra-thin body MOSFETs, multiple-gate MOSFETs, finFETs, or similar devices) require the use of a mid-gap workfunction gate electrode not achievable with doped polysilicon. The use of a metal electrode material can decrease gate resistance (or likewise inner electrode resistance in a trench capacitor) and eliminate polysilicon depletion. Metal gate electrodes can also have mid-gap workfunctions or near band-edge workfunctions. The metals chosen for such applications should be highly compatible with the dielectric materials with which they will share an interface. A high degree of interdiffusion of atomic species between the dielectric layer and electrode and undesirable reactions between the two materials should be avoided.